# RUN: llvm-mc -disassemble -triple=thumbv8.1m.main-none-eabi -mattr=+8msecext -show-encoding %s 2> %t | FileCheck %s
# RUN: FileCheck --check-prefix=WARN < %t %s
# RUN: llvm-mc -disassemble -triple=thumbv8.1m.main-none-eabi -mattr=+mve.fp,+8msecext -show-encoding %s 2> %t | FileCheck %s
# RUN: FileCheck --check-prefix=WARN < %t %s

[0x9f 0xec 0x04 0x0a]
# CHECK: vscclrm {s0, s1, s2, s3, vpr}

[0xdf,0xec,0x06,0x1a]
# CHECK: vscclrm            {s3, s4, s5, s6, s7, s8, vpr} @ encoding: [0xdf,0xec,0x06,0x1a]

[0x9f 0xec 0x0c 0x9a]
# CHECK: vscclrm {s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, vpr}

[0xdf 0xec 0x01 0xfa]
# CHECK: vscclrm {s31, vpr}

[0x9f,0xec,0x04,0x0b]
# CHECK: vscclrm            {d0, d1, vpr}  @ encoding: [0x9f,0xec,0x04,0x0b]

[0x9f,0xec,0x08,0x0b]
# CHECK: vscclrm            {d0, d1, d2, d3, vpr}  @ encoding: [0x9f,0xec,0x08,0x0b]

[0x9f,0xec,0x06,0x5b]
# CHECK: vscclrm            {d5, d6, d7, vpr}  @ encoding: [0x9f,0xec,0x06,0x5b]

[0x88 0xbf]
# CHECK: it    hi

[0xdf 0xec 0x1d 0x1a]
# CHECK: vscclrmhi    {s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31, vpr}

[0xdf,0xec,0x03,0xfa]
# CHECK: vscclrm {s31, d16, vpr} @ encoding: [0xdf,0xec,0x03,0xfa]

[0x9f,0xec,0x40,0x0a]
# CHECK: vscclrm {s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31, d16, d17, d18, d19, d20, d21, d22, d23, d24, d25, d26, d27, d28, d29, d30, d31, vpr} @ encoding: [0x9f,0xec,0x40,0x0a]

# If the list size is zero then we get a list of only vpr, and the Vd register
# doesn't matter.

[0x9f,0xec,0x00,0x0b]
# CHECK: vscclrm {vpr} @ encoding: [0x9f,0xec,0x00,0x0b]

[0xdf,0xec,0x00,0xfb]
# CHECK: vscclrm {vpr} @ encoding: [0x9f,0xec,0x00,0x0b]

[0x9f,0xec,0x00,0x0a]
# CHECK: vscclrm {vpr} @ encoding: [0x9f,0xec,0x00,0x0a]

[0xdf,0xec,0x00,0xfa]
# CHECK: vscclrm {vpr} @ encoding: [0x9f,0xec,0x00,0x0a]

# In double-precision if Vd+size goes past 31 the excess registers are ignored
# and we get a warning.

[0x9f,0xec,0xfe,0x0b]
# WARN: [[@LINE-1]]:2: warning: potentially undefined instruction encoding
# CHECK: vscclrm {d0, d1, d2, d3, d4, d5, d6, d7, d8, d9, d10, d11, d12, d13, d14, d15, d16, d17, d18, d19, d20, d21, d22, d23, d24, d25, d26, d27, d28, d29, d30, d31, vpr} @ encoding: [0x9f,0xec,0x40,0x0b]

[0xdf,0xec,0x04,0xfb]
# WARN: [[@LINE-1]]:2: warning: potentially undefined instruction encoding
# CHECK: vscclrm {d31, vpr} @ encoding: [0xdf,0xec,0x02,0xfb]

# In single-precision if Vd+size goes past 63, or if the encoding suggests half
# a d registers, then the excess registers are ignored and we get a warning.

[0x9f,0xec,0xff,0x0a]
# WARN: [[@LINE-1]]:2: warning: potentially undefined instruction encoding
# CHECK: vscclrm {s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31, d16, d17, d18, d19, d20, d21, d22, d23, d24, d25, d26, d27, d28, d29, d30, d31, vpr} @ encoding: [0x9f,0xec,0x40,0x0a]

[0xdf,0xec,0x02,0xfa]
# WARN: [[@LINE-1]]:2: warning: potentially undefined instruction encoding
# CHECK: vscclrm {s31, vpr} @ encoding: [0xdf,0xec,0x01,0xfa]

[0xdf,0xec,0x23,0xfa]
# WARN: [[@LINE-1]]:2: warning: potentially undefined instruction encoding
vscclrm {s31, d16, d17, d18, d19, d20, d21, d22, d23, d24, d25, d26, d27, d28, d29, d30, d31, vpr} @ encoding: [0xdf,0xec,0x21,0xfa]